1 Field of the Invention
The present invention relates to a semiconductor device with an alignment mark and a manufacturing method thereof, and particularly to a semiconductor device with an alignment mark and a manufacturing method thereof facilitating alignment mark detection and improving alignment accuracy.
2 Description of the Background Art
FIG. 21 is a section of a semiconductor device having a multilayer interconnection structure. In this semiconductor device, a gate interconnection 3 is formed on a semiconductor substrate 1 with an insulation film posed therebetween. Gate interconnection 3 is placed between source/drain regions 4 formed in semiconductor substrate 1.
A first metal interconnection layer 6, of aluminum or the like, is formed on gate interconnection 3 with an interlayer insulation film 5 posed therebetween. First metal interconnection layer 6 is electrically connected with source/drain region 4 via a contact hole 5a.
A second metal interconnection layer 8, of aluminum or the like, is formed on first metal interconnection layer 6 with an interlayer insulation film 7 posed therebetween. Second metal interconnection layer 8 is electrically connected with first metal interconnection layer 6 via a contact hole 7a, and covered with a protective film 11.
In this structure, precise interconnections between first metal interconnection layer 6 and gate interconnection 3 and second metal interconnection layer 8 and first metal interconnection layer 6 are necessary. Therefore, the precise formation of a resist film, which is used for the patterning of first metal interconnection layer 6 and second metal interconnection layer 8, is required.
Conventionally an alignment mark is used for the positioning of the resist film for the patterning of first metal interconnection layer 6 and second interconnection layer 8. As an example, an alignment mark formed in interlayer insulation film 5 for the positioning of the resist film used for the patterning of first metal interconnection layer 6 will be described referring to FIGS. 22 and 23.
With reference to FIGS. 22 and 23, an alignment mark 4 formed in interlayer insulation film 5 is formed as a recess portion being rectangular in plan and having two sets of opposing sidewalls 4a, 4b and 4c, 4d. In recent years, for the improvement of a coverage, first metal interconnection layer 6 has been deposited on alignment mark 4 by an interconnection process using a high temperature aluminum sputtering technique.
The high temperature sputtering technique is different from a normal sputtering technique in that a heat treatment at 300.degree. C.-600.degree. C. is performed during or after the deposition of a film.
As a result, an aluminum grain 6A grows large as shown in FIGS. 22 and 23 and an aluminum material flows in the recess portion, whereby a gentle-sloped side surface is formed in a region enclosed and designated by A in FIG. 23.
At the detection of a resist film side alignment mark used for the patterning of first metal interconnection layer 6, signals P1 and P3 corresponding to side surfaces 9a and 9b of resist film side alignment mark 9 can easily be located because of high strength and distinct peaks of these signals as can be seen from FIG. 24 showing detection signal strength measured at a section taken along a line X1-X1' of FIG. 22.
On the other hand, signals P2 and P4 corresponding to side surfaces 6a and 6b of first metal interconnection layer 6, which are deposited on sidewalls 4a and 4b of alignment mark 4 in the insulation layer, cannot be located accurately because of their low strength and indistinct peaks. Therefore, accurate measurements of a distance L1 between signal P1 and signal P2 and a distance L2 between signal P3 and signal P4 cannot be obtained.
FIG. 25 shows detection signal strength measured at a section taken along a line X2-X2' of FIG. 22 and FIG. 26 shows detection signal strength measured at a section taken along a line X3-X3' of FIG. 22. As can be seen from the comparison of these drawings, a largely grown aluminum grain 6A causes the fluctuation of the detected locations of signals P2 and P4 corresponding to side surfaces 6a and 6b of first metal interconnection layer 6 deposited on sidewalls 4a and 4b of alignment mark 4, depending on the measurement points.
Above described problems hinder the easy and accurate detection of the locations of signals P2 and P4 corresponding to side surfaces 6a and 6b of first metal interconnection layer 6 deposited on sidewalls 4a and 4b of alignment mark 4.